1. Field of the Invention
The present invention relates to an image display device to which a digital picture signal is inputted and a driver circuit therefore. More particularly, the present invention is directed to a driver circuit for an image display device in which an occupied area of the driver circuit is reduced, and further. the delay of a digital picture signal to be inputted and the waveform distortion thereof are reduced.
2. Description of the Related Art
In recent years, an image display device in which semiconductor thin films are formed on a glass substrate, in particular an active matrix image display device using thin film transistors (hereinafter referred to as TFTs) has come into wide use. The active matrix image display device (hereinafter referred to as image display device) using the TFTs includes hundreds of thousand to several million TFTs arranged in a matrix form, which control electric charges of respective pixels.
Further, as a recent technique, a polysilicon TFT technique for simultaneously forming a driver circuit by using TFTs at the outside of a pixel array portion. in addition to pixel TFTs constituting pixels, has been developed.
Besides, as the driver circuit, not only one for processing an analog picture signal but also one for processing a digital picture signal is realized.
FIG. 25 shows a structural example of an active matrix type liquid crystal display device as one of the image display device. As shown in FIG. 25. this liquid crystal display device is constituted by a signal line driver circuit 101. a scan line driver circuit 102, a pixel array portion 103, signal lines 104, scan lines 105, pixel TFTs 106. liquid crystals 107, and the like.
FIG. 26 is a view for explaining in detail a structure of a conventional (digital system) signal line driver circuit for processing a digital picture signal. FIG. 27 is a timing chart corresponding to FIG. 26. Here, an example of an image display device having k (horizontal)×l (vertical) pixels will be described. Although a case where a digital picture signal has three bits is exemplified for facilitating the explanation, the number of bits in an actual image display device is not limited to 3. Besides, FIGS. 26 and 27 shows a specific example of k=640.
The conventional signal line driver circuit has the following structure. This is constituted by a shift register to which a clock signal (CLK) and a start pulse are inputted and which sequentially shifts the pulse, first storage circuits (LAT 1) for sequentially storing digital picture signals by the output of the shift register, second storage circuits (LAT 2) for storing the outputs of the first storage circuits in accordance with input of a latch signal (LP), and D/A converter circuits (DAC) for converting the outputs of the second storage circuits into analog signals. Here, a latch circuit is used for the storage circuit.
The number of shift register stages (corresponding to the number of DFFs shown in FIG. 26) becomes k+1. Output signals of the shift register become control signals (SR-001 to SR-640) of the first storage circuits (LAT 1) directly or through buffers. The first storage circuits (LAT 1) store digital picture signals (D0 to D2) in accordance with the output timing of the control signals. Here, as the first storage circuits (LAT 1), 3 (number of bits)×k (number of horizontal signal lines) circuits become necessary. Also as the second storage circuits (LAT 2), 3×k circuits become necessary.
The clock signal (CLK) for the shift register, the start pulse (SP), the digital picture signals (D0 to D2), and the latch signal (LP) are inputted to the signal line driver circuit. First, the start pulse (SP) and the clock signal (CLK) are inputted to the shift register, and the pulse is sequentially shifted. Outputs (SR-001 to SR-640 in FIG. 26) of the shift register become, as shown in FIG. 27, pulses in which the clock signal (CLK) is shifted by the period. The first storage circuits (LAT 1) are operated by the output signals of the shift register, and store the digital picture signals inputted at that time. The pulse of the shift register is shifted for one line, so that the digital picture signals of the one line are stored in the first storage circuits (LAT 1). (L1-001 to L1-640 in FIG. 26, however, for simplification, they are collectively shown without discriminating the bits).
Next, the latch signal (LP) is inputted in a horizontal retrace period. By this latch signal, the second storage circuits (LAT 2) operate, and the picture signals (L1-001 to L1-640 in FIGS. 26 and 27) stored in the first storage circuits (LAT 1) are stored in the second storage circuits (LAT 2). When the horizontal retrace period is completed and a next horizontal scan period starts, the shift register again starts the operation. On the other hand, the digital picture signals (L2-001 to L2-640 in FIGS. 26 and 27, however, for simplification, they are collectively shown without discriminating the bits) stored in the second storage circuits (LAT 2) are converted into analog signals by the D/A converter circuits (DAC). The analog signals are transmitted to the signal lines (S001 to S640 in FIG. 26), and are further written into the corresponding pixels through the pixel TFTs which are switched on by the scan line driver circuit.
By the above operation, the image display device writes the picture signals into the pixels and carries out a display.
As compared with an analog system, the digital system driver circuit as described above has a defect that its occupied area is very large. Although the digital system has a merit that a signal can be expressed by two values of “Hi” and “Lo”, the amount of data becomes large instead, and it becomes a serious obstacle from the viewpoint of miniaturization in constructing the image display device. The increase in area of the image display device has problems that the increase in its manufacturing costs is caused and the profit of a manufacturing company is made worse.
Besides, as the amount of information to be treated rapidly increases in recent years, an attempt to increase the number of pixels and to improve the definition of pixels has been made. However, as the number of pixels is increased, the driver circuit is also enlarged, and it is desired that the area of the driver circuit is further reduced.
Here, examples of generally used display resolution of a computer are set forth below with the number of pixels and standard name.
number of pixelsstandard name640 × 480VGA800 × 600SVGA1024 × 768 XGA1280 × 1024SXGA1600 × 1200UXGA
For example, in the case where the SXGA standard is cited as an example, when the number of bits is 8, 10240 first storage circuits, 10240 second storage circuits, and 10240 D/A converter circuits become necessary in the foregoing conventional driver circuit for 1280 signal lines. Besides, a high definition television receiver such as a high vision TV (HDTV) becomes popular, and a high definition image becomes necessary for not only the field of a computer but also the field of an Audio and Visual. In USA, ground wave digital broadcasting starts, and also in Japan, the age of digital broadcasting starts. In the digital broadcasting, the number of pixels of 1920×1080 is dominant, and prompt reduction in the area occupied by the driver circuit is demanded.
On the other hand, as shown in FIG. 26 as well, in the conventional digital system driver circuit, since it is necessary that signal transmission lines for supplying the digital picture signals (D0 to D2) are connected to all the first storage circuits (LAT 1), the extension of the wiring becomes very long. As a result, a load to the signal transmission line, such as load capacitance or resistance, becomes large, and the delay of the digital picture signal and the waveform distortion become large. This tendency becomes remarkable when the number of pixels increases, and there occurs a problem that a display based on accurate digital picture signals becomes difficult.